-- Contador do Segundo

library ieee;
use ieee.std_logic_1164.all;
use work.PCT_SEGUNDO.all;

entity SEGUNDO is
port(
		CLK, CLR: in std_logic;
		PRESETS1: in std_logic_vector(3 downto 0); -- 4
		PRESETS2: in std_logic_vector(3 downto 0); -- 2
		S_SEGUNDO: in std_logic;
		LOAD: in std_logic;
		INC: in std_logic;
		S1, S2: out std_logic_vector(6 downto 0);
		QCLK: out std_logic
	);
end SEGUNDO;

architecture DT_FLOW of SEGUNDO is
signal Q_DIV : std_logic; -- 1Hz
signal S_COUNT1 : std_logic_vector(3 downto 0);
signal S_COUNT2 : std_logic_vector(3 downto 0);
signal Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1 : std_logic;
signal S_INC : std_logic;
signal RST : std_logic;

begin
	S_INC <= INC AND LOAD AND CLR;
	RST <= S_INC OR NOT(S_SEGUNDO);

	COUNT_DEC_BCD1 : COUNT_DEC_BCD port map (CLK, RST, "0000", Q4, Q3, Q2, Q1);
	COUNT_5_BCD2 : COUNT_5_BCD port map (Q4, RST, "0000", Q8, Q7, Q6, Q5);
	
	QCLK <= Q7;
	
	S_COUNT1(3) <= Q4;
	S_COUNT1(2) <= Q3;
	S_COUNT1(1) <= Q2;
	S_COUNT1(0) <= Q1;
	
	S_COUNT2(3) <= Q8;
	S_COUNT2(2) <= Q7;
	S_COUNT2(1) <= Q6;
	S_COUNT2(0) <= Q5;
	
	BCD_7SEG1 : BCD_7SEG port map (S_COUNT1,S1);
	BCD_7SEG2 : BCD_7SEG port map (S_COUNT2,S2);	

end DT_FLOW;